This invention relates to a standard cell LSI layout method using standard cells.
As a technique of LSI layout, a layout by standard cell LSI is known, which is realized in the following procedure. (a) Standard cells having various logic functions (nand, nor, etc.) are stored in a library. (b) The gates described in a logic diagram are replaced by the standard cells stored in the library. (c) The replaced cells are arranged linearly in plural rows. (d) The standard cells are routed in accordance with the net list of gates in the logic diagram, using the area called a channel between rows as the routing area.
The standard cells to be used contain patterns of the power and ground wires therein. To supply power to the standard cells contained in the standard cell rows, it is necessary to place the standard cells linearly by combining the patterns of the power and ground wires of the standard cells contained in the same row. In order to combine the patterns of the power and ground wires, the position of a standard cell is limited within its cell row. Accordingly, if there is a deviation in the routing density (that is, the number of wires in the routing area) in the upper and lower channels adjacent to the cell row, a vacant area which is disadvantageous for reducing the chip area occurs. As a result, the LSI chip area is increased.